1. Field of the Invention
The present invention relates to an image processor loaded on a digital camera or the like.
2. Description of the Background Art
FIG. 10 is a schematic block diagram of a general digital still camera 100. In the digital still camera 100, an analog image signal picked up with an image pickup sensor 105 such as a CCD sensor or a CMOS sensor is converted to a digital signal and thereafter subjected to various image processing such as gamma correction, color space conversion, pixel interpolation and edge enhancement in an image processing part 106, as shown in FIG. 10. Image data subjected to such image processing is finder-displayed on a liquid crystal monitor 109, compression-coded in the JPEG (joint photographic experts group) system or the TIFF (tag image file format) and stored in a storage medium (memory card) 110 formed by a nonvolatile memory or the like, or output to an external device such as a personal computer or a printer through an interface 111. Referring to FIG. 10, numeral 101 denotes an optical lens, numeral 102 denotes a color correction filter, numeral 103 denotes an optical LPF (low-pass filter), numeral 104 denotes a color filter array, and numeral 107 denotes a driving part driving/controlling the image pickup sensor 105.
In general, image processing in the image processing part 106 is classified into image processing such as gamma correction or color space conversion in units of single pixels and image processing such as pixel interpolation or edge enhancement in units of multiple pixels. In the image processing in units of multiple pixels, processed data of a specific pixel is created from a plurality of pixel data surrounding the specific pixel, and hence pixel data of a plurality of horizontal lines must be stored in line memories (not shown). Therefore, a plurality of line memories each having capacity at least corresponding to the number of horizontal pixels of the image pickup sensor 105 are prepared in general. However, the pixel size (pixel number) of the image pickup sensor 105 is not uniform. When the capacity of the line memories is matched with a popular pixel size, therefore, the image processing in units of multiple pixels cannot be executed on an image sensor having a larger pixel size. When the capacity of the line memories built into an image processing circuit integrated into a chip is increased, power consumption as well as the chip size and the manufacturing cost are disadvantageously increased.
FIG. 11 is a schematic block diagram for illustrating an image processing method solving the aforementioned problem. Referring to FIG. 11, it is assumed that raw image data input in the image processing part 106 has 3072 horizontal pixels exceeding the capacity, corresponding to 2048 horizontal pixels, of line memories (not shown) provided in an RPU (real-time processing unit) 106A of the image processing part 106. The image processing part 106 comprises the RPU 106A image-processing progressive (sequential scanning) type raw image data in real time. The RPU 106A is integrated into a chip, and comprises pixel processing means 106Aa performing image processing such as gamma correction, pixel interpolation and color space conversion on the raw image data transferred from a raw image data buffer 108a. 
First, raw image data picked up with the image pickup sensor 105 is temporarily transferred to and stored in the raw image data buffer 108a provided on a memory 108 (ST100). At subsequent steps ST101 and ST102, pixel data are read from the raw image data buffer 108a as divided image data A1 having 2048 horizontal pixels and divided image data A2 having 1024 horizontal pixels and transferred to the RPU 106A. At the step ST101, the divided image data A1 is read from the raw image data buffer 108a, transferred to the pixel processing means 106Aa and subjected to image processing in units of single pixels and in units of multiple pixels, and thereafter transferred to and stored in a processed data buffer 108b. At the subsequent step ST102, the divided image data A2 is read from the raw image data buffer 108a, transferred to the pixel processing means 106Aa and subjected to image processing, and thereafter transferred to and stored in another processed data buffer 108c. 
At a subsequent step ST103, divided image data A1a and A2a stored in the processed data buffers 108b and 108c respectively are transferred to image combining means 106B and thereafter combined with each other into image data of one frame.
A CPU 106C compression-codes the image data output from the image combining means 106B by the JPEG system or the like (ST104), and stores the same in the storage medium (memory card) 110 (ST105).
In such image processing, however, the RPU 106A must store a plurality of lines of the divided image data A1 and A2 in the line memory when the pixel processing means 106Aa performs the processing in units of multiple pixels, and temporally independently process the divided image data A1 and A2. Thus, the raw image data of one frame is temporarily stored in the raw image data buffer 108a so that the divided image data A1 and A2 are thereafter transferred to the RPU 106A, and hence the capacity of the memory 108 is increased to disadvantageously increase the cost as well as the image processing time. Therefore, the processing time required for ending writing of the compression-coded image in the storage medium 110 after the operator presses a shutter release button is disadvantageously increased, for example.